http://ozlabs.org/
MIPS-related developments
www.linux-mips.org
ARM-related Linux development
www.arm.linux.org.uk
Primary home for a huge collection of open-source projects
http://sourceforge.net
Mailing Lists
Hundreds, if not thousands, of mailing lists cater to every aspect of Linux and open-source development. Here are a few to consider. Make sure you familiarize yourself with mailing list etiquette before posting to these lists.
Most of these lists maintain archives that are searchable. This is the first place that you should consult. In a great majority of the cases, your question has already been asked and answered. Start your reading here, for advice on how to best use the public mail lists:
The Linux Kernel Mailing List FAQ
www.tux.org/lkml
List server serving various Linux kernel-related mail lists
http://vger.kernel.org
Linux Kernel Mailingvery high volume, kernel development only
http://vger.kernel.org/vger-lists.html#linux-kernel
Linux News and Developments
Many news sites are worth browsing occasionally. Some of the more popular are listed here.
LinuxDevices.com
www.linuxdevices.com
PowerPC News and other information
http://penguinppc.org
General Linux News and Developments
www.lwn.net
Open Source Insight and Discussion
The following public website contains useful information and education focusing on legal issues around open source.
www.open-bar.org
Appendix F. Sample BDI-2000 Configuration File
; bdiGDB configuration file for the UEI PPC 5200 Board
; Revision 1.0
; Revision 1.1 (Added serial port setup)
; -----------------------------------------------------------
; 4 MB Flash (Am29DL323)
; 128 MB Micron DDR DRAM
;
[INIT]
; init core register
WREG MSR 0x00003002 ;MSR : FP,ME,RI
WM32 0x80000000 0x00008000 ;MBAR : internal registers at 0x80000000
; Default after RESET, MBAR sits at 0x80000000
; because it's POR value is 0x0000_8000 (!)
WSPR 311 0x80000000 ; MBAR : save internal register offset
; SPR311 is the MBAR in G2_LE
WSPR 279 0x80000000 ;SPRG7: save internal memory offsetReg: 279
; Init CDM (Clock Distribution Module)
; Hardware Reset config {
; ppc_pll_cfg[0..4] = 01000b
: XLB:Core -> 1:3
: Core:f(VCO) -> 1:2
: XLB:f(VCO) -> 1:6
;
; xlb_clk_sel = 0 -> XLB_CLK=f(sys) / 4 = 132 MHz
;
; sys_pll_cfg_1 = 0 -> NOP
; sys_pll_cfg_0 = 0 -> f(sys) = 16x SYS_XTAL_IN = 528 MHz
; }
;
; CDM Configuration Register
WM32 0x8000020c 0x01000101
; enable DDR Mode
; ipb_clk_sel = 1 -> XLB_CLK / 2 (ipb_clk = 66 MHz)
