; pci_clk_sel = 01 -> IPB_CLK/2
; CS0 Flash
WM32 0x80000004 0x0000ff00 ;CS0 start = 0xff000000 - Flash memory is on
CS0
WM32 0x80000008 0x0000ffff ;CS0 stop = 0xffffffff
; IPBI Register and Wait State Enable
WM32 0x80000054 0x00050001 ;CSE: enable CS0, disable CSBOOT,
;Wait state enable
; CS2 also enabled
WM32 0x80000300 0x00045d30 ;BOOT ctrl
; bits 0-7: WaitP (try 0xff)
; bits 8-15: WaitX (try 0xff)
; bit 16: Multiplex or non-mux'ed (0x0 = non-muxed)
; bit 17: reserved (Reset value = 0x1, keep it)
; bit 18: Ack Active (0x0)
; bit 19: CE (Enable) 0x1
; bits 20-21: Address Size (0x11 = 25/6 bits)
; bits 22:23: Data size field (0x01 = 16-bits)
; bits 24:25: Bank bits (0x00)
; bits 26-27: WaitType (0x11)
; bits 28: Write Swap (0x0 = no swap)
; bits 29: Read Swap (0x0 = no swap)
; bit 30: Write Only (0x0 = read enable)
; bit 31: Read Only (0x0 = write enable)
; CS2 Logic Registers
WM32 0x80000014 0x0000e00e
WM32 0x80000018 0x0000efff
; LEDS:
; LED1 - bits 0-7
; LED2 - bits 8-15
; LED3 - bits 16-23
; LED4 - bits 24-31
; off = 0x01
; on = 0x02
; mm 0xe00e2030 0x02020202 1 (all on)
; mm 0xe00e2030 0x01020102 1 (2 on, 2 off)
WM32 0x80000308 0x00045b30 ; CS2 Configuration Register
; bits 0-7: WaitP (try 0xff)
; bits 8-15: WaitX (try 0xff)
; bit 16: Multiplex or non-mux'ed (0x0 =
non-muxed)
; bit 17: reserved (Reset value = 0x1, keep it)
; bit 18: Ack Active (0x0)
; bit 19: CE (Enable) 0x1
; bits 20-21: Address Size (0x10 = 24 bits)
; bits 22:23: Data size field (0x11 = 32-bits)
; bits 24:25: Bank bits (0x00)
; bits 26-27: WaitType (0x11)
; bits 28: Write Swap (0x0 = no swap)
; bits 29: Read Swap (0x0 = no swap)
; bit 30: Write Only (0x0 = read enable)
; bit 31: Read Only (0x0 = write enable)
WM32 0x80000318 0x01000000 ; Master LPC Enable
;
; init SDRAM controller
;
; For the UEI PPC 5200 Board,
; Micron 46V32M16-75E (8 MEG x 16 x 4 banks)
; 64 MB per Chip, for a total of 128 MB
; arranged as a single 'space' (i.e 1 CS)
; with the following configuration:
; 8 Mb x 16 x 4 banks
; Refresh count 8K
; Row addressing: 8K (A0..12) 13 bits
; Column addressing: 1K (A0..9) 10 bits
; Bank Addressing: 4 (BA0..1) 2 bits
; Key Timing Parameters: (-75E)
; Clockrate (CL=2) 133 MHz
; DO Window 2.5 ns
; Access Window: +/- 75 ns
; DQS - DQ Skew: +0.5 ns
; t(REFI): 7.8 us MAX
;
; Initialization Requirements (General Notes)
; The memory Mode/Extended Mode registers must be
; initialized during the system boot sequence. But before
; writing to the controller Mode register, the mode_en and
; cke bits in the Control register must be set to 1. After
; memory initialization is complete, the Control register
; mode_en bit should be cleared to prevent subsequent access
; to the controller Mode register.
; SDRAM init sequence
; 1) Setup and enable chip selects
; 2) Setup config registers
; 3) Setup TAP Delay
; Setup and enable SDRAM CS
WM32 0x80000034 0x0000001a ;SDRAM CS0, 128MB @ 0x00000000
WM32 0x80000038 0x08000000 ;SDRAM CS1, disabled @ 0x08000000
