Embedded Linux Primer: A Practical, Real-World Approach

/* options as well. See miscLib/main.c.  */
/*------------------------------------- */
bl      invalidate_icache
bl      invalidate_dcache
/*-------------------------------------- */
/* Enable two 128MB cachable regions.     */
/*-----------------------------------    */
addis   r4,r0,0x8000
addi    r4,r4,0x0001
mticcr  r4                        /* instruction cache */
isync
addis   r4,r0,0x0000
addi    r4,r4,0x0000
mtdccr  r4                        /* data cache */

The first code to execute in start.S for the 405GP processor starts about a third of the way into the source file, where a handful of processor registers are cleared or set to sane initial values. The instruction and data caches are then invalidated, and the instruction cache is enabled to speed up the initial load. Two 128MB cacheable regions are set up, one at the high end of memory (the Flash region) and the other at the bottom (normally the start of system DRAM). U-Boot eventually is copied to RAM in this region and executed from there. The reason for this is performance: Raw reads from RAM are an order of magnitude (or more) faster than reads from Flash. However, for the 4 xx CPU, there is another subtle reason for enabling the instruction cache, as we shall soon discover.

7.4.4. Board-Specific Initialization

The first opportunity for any board-specific initialization comes in .../cpu/ppc4xx/start.S just after the cacheable regions have been initialized. Here we find a call to an external assembler language routine called ext_bus_cntlr_init.

bl ext_bus_cntlr_init /* Board specific bus cntrl init */

This routine is defined in .../board/ep405/init.S, in the new board-specific directory for our board. It provides a hook for very early hardware-based initialization. This is one of the files that has been customized for our EP405 platform. This file contains the board-specific code to initialize the 405GP's external bus controller for our application. Listing 7-7 contains the meat of the functionality from this file. This is the code that initializes the 405GP's external bus controller.

Listing 7-7. External Bus Controller Initialization

 .globl  ext_bus_cntlr_init
ext_bus_cntlr_init:
   mflr      r4             /* save link register          */
   bl        ..getAddr
..getAddr:
   mflr      r3            /* get _this_ address           */
   mtlr      r4            /* restore link register        */
   addi      r4,0,14       /* prefetch 14 cache lines...   */
   mtctr     r4            /* ...to fit this function      */
                           /* cache (8x14=112 instr)       */
..ebcloop:
   icbt      r0,r3         /* prefetch cache line for [r3] */
   addi      r3,r3,32      /* move to next cache line      */
   bdnz      ..ebcloop     /* continue for 14 cache lines  */
    /*---------------------------------------------------  */
    /* Delay to ensure all accesses to ROM are complete    */
    /* before changing  bank 0 timings                     */
    /* 200usec should be enough.                           */
    /* 200,000,000 (cycles/sec) X .000200 (sec) =          */
    /* 0x9C40 cycles                                       */
    /*---------------------------------------------------  */
    addis    r3,0,0x0
    ori      r3,r3,0xA000 /* ensure 200usec have passed t  */
    mtctr    r3
..spinlp:
    bdnz     ..spinlp      /* spin loop                    */
    /*----------------------------------------------------*/
    /* Now do the real work of this function              */
    /* Memory Bank 0 (Flash and SRAM) initialization      */
    /*----------------------------------------------------*/
    addi     r4,0,pb0ap         /* *ebccfga = pb0ap;      */
    mtdcr    ebccfga,r4
    addis    r4,0,EBC0_B0AP@h   /* *ebccfgd = EBC0_B0AP;  */
    ori      r4,r4,EBC0_B0AP@l
    mtdcr    ebccfgd,r4
    addi     r4,0,pb0cr         /* *ebccfga = pb0cr;      */
    mtdcr    ebccfga,r4
    addis    r4,0,EBC0_B0CR@h   /* *ebccfgd = EBC0_B0CR;  */
    ori      r4,r4,EBC0_B0CR@l
    mtdcr    ebccfgd,r4
    /*----------------------------------------------------*/
    /* Memory Bank 4 (NVRAM & BCSR) initialization    */
    /*----------------------------------------------------*/
    addi     r4,0,pb4ap         /* *ebccfga = pb4ap;      */
    mtdcr    ebccfga,r4
    addis    r4,0,EBC0_B4AP@h   /* *ebccfgd = EBC0_B4AP;  */
    ori      r4,r4,EBC0_B4AP@l
    mtdcr    ebccfgd,r4
    addi     r4,0,pb4cr         /* *ebccfga = pb4cr;      */
    mtdcr    ebccfga,r4