memory subsystem, the processor generates a submultiple of the main CPU clock to feed to the SDRAM subsystem. You need to configure this clocking ratio for your particular CPU and SDRAM combination.
The processor and memory subsystem clocks must be correctly configured for your SDRAM to work properly. Your processor manual contains a section on clock setup and management, and you must consult this to properly set up your particular board design.
The AMCC 405GP is typical of processors of its feature set. It takes a single crystal-generated clock input source and generates several internal and external clocks required of its subsystems. It generates clocks for the CPU, PCI interface, Onboard Peripheral Bus (OPB), Processor Local Bus (PLB), Memory Clock (MemClk), and several internal clocks for peripherals such as timer and UART blocks. A typical configuration might look like those in Table D-1.
Table D-1. Typical PPC405GP Clock Configuration
| Clock | Rate | Comments |
|---|---|---|
| Crystal reference | 33MHz | Fundamental reference supplied to processor |
| CPU clock | 133MHz | Derived from processor's internal PLL, controlled by hardware pin strapping and register settings. |
| PLB clock | 66MHz | Derived from CPU clock and configured via hardware pin strapping and register settings. Used for internal processor local bus data interchange among its high-speed modules. |
| OPB clock | 66MHz | Derived from PLB clock and configured via register settings. Used for internal connection of peripherals that do not need high-speed connection. |
| PCI clock | 33MHz | Derived from PLB clock and configured via register settings. |
| MemClk | 100MHz | Drives the SDRAM chips directly. Derived from CPU clock and configured via register settings. |
Decisions about clock setup normally must be made at hardware design time. Pin strapping options determine initial clock configurations upon application of power to the processor. Some control over derived clocks is often available by setting divider bits accessible through processor internal registers dedicated to clock and subsystem control. In the example we present here based on the 405GP, final clock configuration is determined by pin strapping and firmware configuration. It is the bootloader's responsibility to set the initial dividers and any other clock options configurable via processor register bits very early after power is applied.
D.3. SDRAM Setup
After the clocks have been configured, the next step is to configure the SDRAM controller. Controllers vary widely from processor to processor, but the end result is always the same: You must provide the correct clocking and timing values to enable and optimize the performance of the SDRAM subsystem.
As with other material in this book, there is no substitute for detailed knowledge of the hardware you are trying to configure. This is especially so for SDRAM. It is beyond the scope of this appendix to explore the design of SDRAM, but some basics must be understood. Many manufacturers' data sheets on SDRAM devices contain helpful technical descriptions. You are urged to familiarize yourself with the content of these data sheets. You don't need a degree in hardware engineering to understand what must be done to properly configure your SDRAM subsystem, but you need to invest in some level of understanding.
Here we examine how the SDRAM controller is configured on the 405GP processor as configured by the U- Boot bootloader we covered in Chapter 7, 'Bootloaders.' Recall from Chapter 7 that U-Boot provides a hook for SDRAM initialization from the assembly language startup code found in start.S in the 4xx-specific cpu directory. Refer back to Section 7.4.4 'Board-Specific Initialization' in Chapter 7. Listing D-1 reproduces the sdram_init() function from U-Boot's .../cpu/ppc4xx/sdram.c file.
Listing D. ppc4xx sdram_init() from U-Boot
01 void sdram_init(void)
02 {
03 ulong sdtr1;
04 ulong rtr;
05 int i;
06
07 /*
08 * Support for 100MHz and 133MHz SDRAM
09 */
10 if (get_bus_freq(0) > 100000000) {
11 /*
12 * 133 MHz SDRAM
13 */
14 sdtr1 = 0x01074015;
15 rtr = 0x07f00000;
16 } else {
17 /*
18 * default: 100 MHz SDRAM
19 */
20 sdtr1 = 0x0086400d;
21 rtr = 0x05f00000;
