22 }
23
24 for (i=0; i<N_MB0CF; i++) {
25 /*
26 * Disable memory controller.
27 */
28 mtsdram0(mem_mcopt1, 0x00000000);
29
30 /*
31 * Set MB0CF for bank 0.
32 */
33 mtsdram0(mem_mb0cf, mb0cf[i].reg);
34 mtsdram0(mem_sdtr1, sdtr1);
35 mtsdram0(mem_rtr, rtr);
36
37 udelay(200);
38
39 /*
40 * Set memory controller options reg, MCOPT1.
41 * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
42 * read/prefetch.
43 */
44 mtsdram0(mem_mcopt1, 0x80800000);
45
46 udelay(10000);
47
48 if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
49 /*
50 * OK, size detected -> all done
51 */
52 return;
53 }
54 }
55}
The first action reads the pin strapping on the 405GP processor to determine the design value for the SDRAM clock. In this case, we can see that two possible values are accommodated: 100MHz and 133MHz. Based on this choice, constants are chosen that will be used later in the function to set the appropriate register bits in the SDRAM controller.
Starting on line 24, a loop is used to set the parameters for each of up to five predefined memory sizes. Currently, U-Boot has logic to support a single bank of memory sized at 4MB, 16MB, 32MB, 64MB, or 128MB. These sizes are defined in a table called mb0cf in .../cpu/ppc4xx/sdram.c. The table associates a constant with each of these memory sizes, based on the value required in the 405GP memory bank configuration register. The loop does this:
for (i = each possible memory bank size, largest first) {
select timing constant based on SDRAM clock speed;
disable SDRAM memory controller;
configure bank 0 with size[i], timing constants[i];
re-enable SDRAM memory controller;
run simple memory test to dynamically determine size;
/* This is done using get_ram_size() */
if (tested size == configured size) done;
}
This simple logic simply plugs in the correct timing constants in the SDRAM controller based on SDRAM clock speed and configured memory bank size from the hard-coded table in U-Boot. Using this explanation, you can easily correlate the bank configuration values using the 405GP reference manual. For a 64MB DRAM size, the memory bank control register is set as follows:
Memory Bank 0 Control Register = 0x000a4001
The PowerPC 405GP User's Manual describes the fields in Table D-2 for the memory bank 0 control register.
Table D-2. 405GP Memory Bank 0-3 Configuration Register Fields
| Field | Value | Comments |
|---|---|---|
| Bank Address (BA) | 0x00 | Starting memory address of this bank. |
| Size (SZ) | 0x4 | Size of this memory bankin this case, 64MB. |
| Addressing Mode (AM) | 0x2 | Determines the organization of memory, including the number of row and column bits. In this case, Mode 2 = 12 row address bits, and either 9 or 10 column address bits, and up to four internal SDRAM banks. This data is provided in a table in the 405GP user's manual. |
| Bank Enable (BE) | 0x1 | Enable bit for the bank configured by this register. There are four of these memory bank configuration registers in the 405GP. |
The values in this table must be determined by the designer, based on the choice of memory module in use on the board.
Let's look at a timing example for more detail on the timing requirements of a typical SDRAM controller. Assuming a 100MHz SDRAM clock speed and 64MB memory size, the timing constants selected by the sdram_init() function in Listing D-1 are selected as follows:
SDRAM Timing Register = 0x0086400d
