Refresh Timing Register = 0x05f00000
The PowerPC 405GP User's Manual describes the fields in Table D-3 for the SDRAM Timing Register.
Table D-3. 405GP SDRAM Timing Register Fields
| Field | Value | Comments |
|---|---|---|
| CAS Latency (CASL) | 0x1 | SDRAM CAS Latency. This value comes directly from the SDRAM chip specifications. It is the delay in clock cycles required by the chip between issuance of the read command (CAS signal) until the data is available on the data bus. In this case, the 0x1 represents two clock cycles, as seen from the 405GP user's manual. |
| Precharge Command to Next Activate (PTA) | 0x1 | The SDRAM Precharge command deactivates a given row. In contrast, the Activate command enables a given row for subsequent access, such as during a burst cycle. This timing parameter enforces the minimum time between Precharge to a subsequent Activate cycle and is dictated by the SDRAM chip. The correct value must be obtained from the SDRAM chip specification. In this case, 0x1 represents two clock cycles, as determined from the 405GP user's manual. |
| Read/Write to Precharge Command Minimum (CTP) | 0x2 | This timing parameter enforces the minimum time delay between a given SDRAM read or write command to a subsequent Precharge command. The correct value must be obtained from the SDRAM chip specification. In this case, 0x2 represents three clock cycles, as determined from the 405GP user's manual. |
| SDRAM Command Leadoff (LDF) | 0x1 | This timing parameter enforces the minimum time delay between assertion of address or command cycle to bank select cycle. The correct value must be obtained from the SDRAM chip specification. In this case, 0x1 represents two clock cycles, as determined from the 405GP user's manual. |
The final timing parameter configured by the U-Boot example in Listing D-1 is the refresh timing register value. This register requires a single field that determines the refresh interval enforced by the SDRAM controller. The field representing the interval is treated as a simple counter running at the SDRAM clock frequency. In the example here, we assumed 100MHz as the SDRAM clock frequency. The value programmed into this register in our example is 0x05f0_0000. From the PowerPC 405GP User's Manual, we determine that this will produce a refresh request every 15.2 microseconds. As with the other timing parameters, this value is dictated by the SDRAM chip specifications.
A typical SDRAM chip requires one refresh cycle for each row. Each row must be refreshed in the minimum time specified by the manufacturer. In the chip referenced in Section D.4.1, 'Suggestions for Additional Reading,' the manufacturer specifies that 8,192 rows must be refreshed every 64 milliseconds. This requires generating a refresh cycle every 7.8 microseconds to meet the specifications for this particular device.
D.4. Summary
SDRAM devices are quite complex. This appendix presented a very simple example to help you navigate the complexities of SDRAM controller setup. The SDRAM controllers perform a critical function and must be properly set up. There is no substitute to diving into a specification and digesting the information presented. The two example documents referenced in this appendix are excellent starting points.
D.4.1. Suggestions for Additional Reading
AMCC 405GP Embedded Processor User's Manual
AMCC Corporation
www.amcc.com/Embedded/
Micron Technology, Inc.
Synchronous DRAM MT48LC64M4A2 Data Sheet
http://download.micron.com/pdf/datasheets/dram/sdram/256MSDRAM.pdf
Appendix E. Open Source Resources
Source Repositories and Developer Information
Several locations on the Web focus on Linux development. Here is a list of the most important websites for the various architectures and projects:
Primary kernel source tree
www.kernel.org
Primary kernel GIT repository
www.kernel.org/git
PowerPC-related development and mailing lists
